1. Field
Exemplary embodiments of the present invention relate to a semiconductor device designing technology, and more particularly, to a semiconductor device that includes contact plugs and a method for fabricating the semiconductor device.
2. Description of the Related Art
A semiconductor device, for example, a Dynamic Random Access Memory (DRAM) device, has a multi-layer structure where a plurality of constituent elements are stacked. The semiconductor device includes a plurality of contact plugs to couple the constituent elements. Typically, the contact plugs are formed through a series of processes for forming an insulation layer over a substrate where a given structure is formed, selectively etching the insulation layer to form openings that expose the predetermined structure, and filling the openings with a conductive material.
However, because the linewidth (or area) of the openings continuously decreases as the integration degree of a semiconductor device increases, the contact area between the contact plugs and the structure that the contact plugs contact with decreases, and thus, contact resistance increases, which becomes a concern. To solve this concern, a technology for forming a silicide layer on the surface of the structure that contacts with the contact plugs after the openings are formed, and forming a conductive material over the silicide layer to decrease the contact resistance is introduced.
According to the conventional technology, the silicide layer for reducing contact resistance is formed through a series of processes for forming an insulation layer over a substrate that includes a structure to contact with contact plugs, selectively etching the insulation layer to form openings, forming a metal layer along the surface of the structure that includes the openings, performing a thermal treatment to form a silicide layer on the surface of the structure, and removing the remaining metal layer that is left behind without reacting after the thermal treatment.
Although it is desirable to form a silicide layer over the surface of the structure that is exposed through the openings according to the conventional technology, the silicide layer may be formed only on a portion of the exposed surface of the structure during the formation of the silicide layer due to a decrease in the area of the openings (or linewidth) and an increase in the aspect ratio that are caused by increased integration degree. In a worse case, the silicide layer may not be formed at all, because it is difficult to form a metal layer having a uniform and sufficient thickness on the bottom surface of the openings, which is the surface of the structure exposed through the openings, due to the decrease in the area of the openings and an increase in the aspect ratio. Also, because the method of depositing the metal layer is restricted in consideration of step coverage based on the aspect ratio of the openings, there is a concern in that the productivity of semiconductor devices may be deteriorated.
Also, since the process of forming the silicide layer is accompanied by a thermal treatment necessarily, thermal load applied on the pre-established structure is increased, which may be a concern as well.